Researchers Use Hardware to Accelerate Core-to-Core On-Chip Communication

Researchers from North Carolina State University and the Intel Corporation have developed a new way to significantly accelerate core-to-core communication. Their advance relies on hardware to coordinate efforts between cores for multiprocessor operatio …

Researchers from North Carolina State University and the Intel Corporation have developed a new way to significantly accelerate core-to-core communication. Their advance relies on hardware to coordinate efforts between cores for multiprocessor operations.

Many computer functions require multiple processors, or cores, to work together in a coordinated way. Currently, this coordination is achieved by sending and receiving software commands between cores. But this requires cores to read and execute the software, which takes time.

Now researchers have developed a chip design that replaces the software instructions with built-in hardware that coordinates communication between cores, accelerating the process.

“This approach, called the core-to-core communication acceleration framework (CAF), improves communication performance by two to 12 times,” says Yan Solihin, a professor of electrical and computer engineering at NC State and co-author of a paper on the work. “In other words, the execution times – from start to finish – are twice as fast or faster.”

A student walks to class on Centennial CampusThe key to the CAF design is a queue management device (QMD), which is a small device attached to the processor network on a chip. The QMD is capable of simple computational functions and effectively keeps track of communication requests between cores without having to rely on software routines.

The researchers have also found that, because it can perform basic computation, the QMD can be used to aggregate data from multiple cores – expediting some basic computational functions by as much as 15 percent.

“We are now looking at developing other on-chip devices that could accelerate more multi-core computations,” Solihin says.

The paper, “CAF: Core to Core Communication Acceleration Framework,” will be presented at the 25th Annual Conference on Parallel Architectures and Compilation Techniques, being held Sept. 11 to 15 in Haifa, Israel. Lead author of the paper is Yipeng Wang, a former Ph.D. student at NC State. The paper was co-authored by Ren Wang, Andrew Herdrich and James Tsai of Intel Corporation.