Samira Mirbagher Ajorpaz

Biography

Dr. Mirbagher is an assistant professor at the Department of Electrical and Computer Engineering at North Carolina State University. She received her BS in computer engineering from University of Isfahan in 2014 and her PhD in Computer Science from Texas A&M University in 2019. She is a 2020 University of California Postdoctoral Fellow in the Computer Science and Engineering Department at the University of California San Diego. She was also, a 2021 MIT ECE Rising Star.

Her research is centered at the intersection of computer architecture, computer systems security, and machine learning with a focus on designing fast, energy efficient and secure microarchitectural units with nano-second scale timing margins. She is also interested in streamlining, accelerating, and simplifying the machine learning models for hardware. These improvements include creating smaller, faster, lower power, sustainable and more secure processors, such as those used in mobile phones, desktop, and laptop computers, as well as high performance servers and clouds. The application of her research area has broader impact that extends from ways to gain deeper insights into the workings of the human brain (e.g., research done at Google Brain Lab) or ideas to enhance the design of microprocessors (e.g., research done by chip manufacturers such as Intel Labs) as well as developing formal and theoretical frameworks for high performance, power efficient and secure computing.

Currently she studies pre-silicon security verification of advanced microarchitectural designs, considering the security of application of machine learning in hardware, identifying microarchitectural side channel and adversarial machine learning attacks, and developing of defenses for them. Her recent studies use generative AI to enable hardware to dynamically adapt itself for security, performance, and power efficiency.

Recent publications:

Sayinath Karuppanan, S. Mirbagher Ajorpaz, An Attack on The Speculative Vectorization: Leakage from Higher Dimensional Speculation , arXiv 2023. [ pdf ] [ slide ]

S. Mirbagher Ajorpaz, D. Moghimi, Jeff Collins, G. Pokam, N. Abu-Ghazaleh, and D. Tullsen, Towards a Practical, Pro-active Adaptive Architecture for High Performance & Security.” In proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture, MICRO 2022. [ pdf ] [ slide ]

Brady Testa, S. Mirbagher Ajorpaz and D. A. Jiménez, Dynamic Set Stealing to Improve Cache Performance. In proceedings of the IEEE 34th International Symposium on Computer Architecture and High Performance Computing, SBACPAD 2022. [ pdf ] [ slide ]

E. Garza, G. Chacon, A. Jimborean, A. Ros, S. Mirbagher Ajorpaz, Paul V. Gratz and D. A. Jiménez, Composite Instruction Prefetching. In proceedings of the 40th IEEE International Conference on Computer Design , ICCD 2022. [ pdf ] [ slide ]

S. Mirbagher Ajorpaz, G. Pokam, E. Garza, E. M. Koruyeh, N. Abu-Ghazaleh, and D. A. Jiménez, PerSpectron: Detecting Microarchitectural Footprints of Side Channel Attacks with Perceptron Learning. In proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture, MICRO 2020. [ pdf ] [ slide ]

S. Mirbagher Ajorpaz, E. Garza, G. Pokam, and D. A. Jiménez, CHiRP: Control-flow History Reuse Prediction, In proceedings of 53rd IEEE/ACM International Symposium on Microarchitecture, MICRO 2020. [ pdf ] [ slide ]

E. Garza, S. Mirbagher Ajorpaz, T. A. Khan, and D. A. Jiménez, Bit-level Perceptron Prediction for Indirect Branches, In proceedings of 46th International Symposium on Computer Architecture, ISCA 2019. [ pdf ] [ slide ]

S. Mirbagher Ajorpaz, E. Garza, S. Jindal, and D. A. Jiménez, Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer, In proceedings of 45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018. [ pdf ] [ slide ]